Engineering Approach to CMOS-Logic Optimization Allowing for Internal Capacitances and On-Chip Interconnections

Abstract

The paper is concerned with the method of logical effort, by which alternative logic-circuit realizations can be evaluated without running simulations. It also represents an engineering approach to optimization of CMOS logic networks for area. The method is modified to allow for the influence of logic-gate capacitances and on-chip interconnections in a multiple-input logic circuit. The former factor is significant in the case of small loads. The latter factor becomes increasingly important to the speed of operation as the technology progresses. The modified method is shown to be considerably more accurate than the standard one while retaining simplicity. Estimations by the modified and the standard method are compared with simulations as applied to the logic portion of the ALU and the address decoder in a general-purpose microprocessor. It is demonstrated that the modified method offers a way to implement the devices with a shorter delay and on a smaller area as well as improving accuracy.