Energy-Efficient VLSI Architecture & Implementation of Bi-modal Multi-banked Register-File Organization

Abstract

For the execution of high-end applications of present-day scenario, processor consumes profound energy and its significant fraction is due to intensive register-file access in the processor architecture. Such fraction of energy required by the processor defers to reduce with the advancement of semiconductor technology and thereby, it is essential to design energy-efficient register-file architecture for the contemporary scenario. This paper presents new register-file architecture called the bi-modal multi-banked register-file organization to capture short term reused and short lived operands to alleviate load on register file to read and write. Additionally, instruction decode stage of the processor architecture is restructured to capture the reused and short lived register operands. On incorporating these new features, we have conceived a processor architecture that has been synthesized and post-layout simulated in 180 nm complementary metal-oxide semiconductor (CMOS) technology node. It consumes 35 mW of total power at 200 MHz of clock frequency. The bi-modal multi-banked register-file organization stores a fraction of data bandwidth, which is local to the functional units, resulting in the reduction of cost for supplying data to the execute stage. Subsequently, the proposed architecture is made to execute MiBench benchmark kernels and it showed up to 55% improvement in energy saving over an embedded reduced instruction-set computer (RISC) processor architecture.