Energy-Efficient Transceiver for Wireless NoC

Abstract

Network-on-Chip (NoC) with wireless interconnects is one of the potential solutions to overcome limitations of conventional NoC architectures over far-apart communications in multicore systems. Detailed investigations of Wireless NoC (WNoC) highlight their many benefits. But, idle-state power consumption associated with WI interfaces and routers is significantly high. To reduce the idle-state power consumption, a power gating technique can be incorporated with WNoC architectures. However, power gating can lead to adverse effects like IR drop, short-term sleep/wake up that increase the transient energy consumption specially for burst traffic, and also increases the cumulative settling time to get exact output response from the power gated components. To address these problems, we propose an energy-efficient transceiver for WNoC architecture using power gating. In this paper, we also present the details of techniques that minimizes the impact of power gating on performance. Proposed architecture saves up to 62.50% of idle-state power of WI as compared with traditional WNoC with minimum impacts of power gating method. This saves the overall packet energy on average by 49% compared to regular WNoC. Design considerations for augmenting power gating in WNoC and corresponding overheads are also presented.