Energy-efficient synchronous counter design with minimum hardware overhead

Abstract

The Performance of any VLSI circuit depends on its design architecture, which optimizes power and provides high reliability. To design any circuit with low power, power optimization of circuit at different levels is needed. Most of the system level architectures consists of sequential circuits, design of these circuits plays an pivotal role in reducing overall energy of the system. Counters are basic building blocks in many VLSI applications such as timers, memories, ADCs/DACs, frequency dividers etc. It is observed that design of counters has power overhead because of requirement of high power consumption for the clock signal distribution and undesired activity of flip-flops due to presence of clocks. In this paper we propose an energy efficient design of synchronous counters that reduces the power consumption due to clock distribution for different flip-flops and offers high reliability. The proposed counter design is evaluated and anlayzed in terms of energy in a standard 45nm CMOS technology in CADENCE. The proposed counter design has lower energy requirement than existing counter architectures and the energy reduction is more significant for wide-bit counters.