Energy-Efficient Power Allocation with Buffer Constraint for High-Speed Railway

Abstract

To satisfy the increasing demands for high data-rate service of high-speed railway (HSR) users on the train, the most promising approach is to utilize the two-hop architecture. With this architecture, large amount of data will be transferred to the access point (AP) at which some data may need to be cached when the train approaches the cell edge. In this paper, an energy-efficiency buffer (EEB) power allocation scheme is proposed, which is able to achieve a high energy efficiency under the requirement of buffer size in HSR scenarios. Firstly, the energy-efficiency optimization problem is formulated as a fractional form. Secondly, this non-convex problem is resolved by transforming it into an equivalent one. Then an iterative power allocation algorithm is proposed and the optimal solution is obtained based on it. Finally, we analyze the effect of cache point on energy efficiency (EE) performance of the proposed EEB power allocation scheme. Furthermore, the relationship between the buffer size and EE performance of HSR communication system is presented. Simulation results suggest that the proposed EEB power allocation scheme can achieve the optimal energy-efficient performance.