Energy-Efficient Dynamic Data Encoding for Multi-level STT-MRAM

Abstract

Spin-Torque-Transfer Magnetic RAM (STTMRAM) is a promising candidate for next generation on-chip last level cache memory. Such technology offers non-volatility, excellent scalability, and CMOS process compatibility. Even though multi-level version of such memories offer more capacity than their single-level counterpart, it suffers from high write energy as well as performance overhead. These unwanted characteristics are due to Two-step Transition (TT) and Hard-Transition (HT). In this paper, we propose a dynamic resistance-to-logic state encoding to minimize energy in MLC STT-MRAM based caches. The proposed encoding/decoding scheme are presented algorithmically and at architectural level. Results on PARSEC benchmarks showed an average reduction of 55% in energy as compared to a recently proposed low power encoding approach.