Energy-efficient design of quaternary logic gates and arithmetic circuits using hybrid CNTFET-RRAM technology

Abstract

Multi-valued logic (MVL) extends binary logic by providing a framework to represent complex systems with more than two truth values. MVL was introduced to confront the enormous interconnect issue associated with the binary logic in implementing the presnt day complex nanoelectronic architectures. This paper delves into the circuit design, computational aspects, and practical applications of the quaternary logic system, which is a type of MVL with four truth values. The multi-threshold property of carbon nanotube field-effect-transistors (CNTFETs), combined with the ability of resistive random-access memory (RRAM) to store multiple resistance values, has enabled the design of quaternary logic gates and arithmetic circuits. A new CNTFET-based design architecture has been proposed to implement the quaternary logic compatible with the existing technologies. Quaternary logic gates such as inverter, NAND, and NOR, and quaternary arithmetic circuits including decoder, half adder, and multiplier have been designed. The power-delay-product (PDP) of the proposed quaternary inverter, NAND, NOR, half adder, and multiplier is 62.38%, 93.4%, 80.29%, 14.79%, and 20% less than the least PDP of the quaternary designs under consideration. The static power reduction due to the effecciency of the design architecture and high OFF state resistance offered by integrating RRAM into the logic design was explored.The proposed circuits have been subject to various types of parameter variations to validate thir proper functionality in presence of these variations.