Energy-Efficient and High-Speed Hybrid 1-Bit Full Adder

Abstract

Full adders are one of the best design blocks of the researches to design multiple numbers of applications. This paper presents different types of logic styles of full adders which are been used. The hybrid 1-bit full adder is designed by accepting the different types of logics which are used to get good results. This design is act by applying of cadence virtuoso tools. By using of these logic styles, the capacity and latency of the entire adder are reduced.