Abstract
This paper presents a full custom design of an energy-efficient and high-performance Add-Compare-Select (ACS) unit. The ACS circuit is a main building block in a stateparallel architecture based Viterbi decoder implementation. The proposed ACS circuit is implemented in 90 nm CMOS using static logic. A standard ACS circuit is also implemented for comparison purposes. The proposed ACS circuit provides high throughput rate at 617 Mbps with relatively low energy requirement. By using full-custom design paradigm, both ACS blocks are designed with fewer transistors and the resultant layouts occupy smaller areas.
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