Energy, Performance, and Probability Tradeoffs for Energy-Efficient Probabilistic CMOS Circuits

Abstract

The scaling trend of semiconductor devices has raised several issues such as energy consumption and heat dissipation, as well as the increasing probabilistic behavior of devices. Motivated by the necessity to consider probabilistic approaches to future designs, probabilistic CMOS (PCMOS) based computing has been proposed. PCMOS devices are inherently probabilistic devices that compute correctly with a probability p. This paper investigates the tradeoffs between the energy, speed (or performance), and probability of correctness (p) of PCMOS circuits. For given constraints on p, performance, and energy delay product (EDP), and using analytical models of energy, delay, and p, the optimum values of EDP and probability are found for PCMOS circuits. The analytical models are validated using circuit simulations for PCMOS circuits designed in a 0.13-mum process. The results show that, to minimize EDP, it is preferable to operate PCMOS circuits at lower supply voltages. On the other hand, to maximize p, the highest possible supply voltage under the given constraints is preferable. Our analysis makes it possible to achieve an optimal circuit design that satisfies the p , performance, and EDP requirements for a given application. An analysis of the impact of variations in temperature, threshold voltage, and supply voltage on optimal EDP and probability values is also included.