Energy Optimization of Cache Hierarchy in Multicore Real-Time Systems

Abstract

Computation using single-core processors has hit the power wall on its way of performance improvement. Chip multiprocessor (CMP) architectures, which integrates multiple processing units on a single integrated circuit (IC), have been widely adopted by major vendors like Intel, AMD, IBM and ARM in both general-purpose computers (e.g., [48]) and embedded systems (e.g., [2, 83]). Multicore processors are able to run multiple threads in parallel at lower power dissipation per unit of performance. Despite the inherent advantages, energy conservation is still a primary concern in multicore system optimization. While power consumption is a key concern in designing any computing devices, energy efficiency is especially critical for embedded systems. Real-time systems that run applications with timing constraints require unique considerations. Due to the ever growing demands for parallel computing, real-time systems commonly employ multicore processors nowadays [140, 148].