Abstract
This paper presents a new mixed-signal design technique called supply boosting technique (SBT) and the design of an energy efficient, sub-1 V supply boosted comparator (SBC) in a standard complementary metal oxide semiconductor (CMOS) process. The selected CMOS process does not allow sub-1 V operation with a wide input range due to high threshold voltage (high-VTH) of MOS transistors (+0.8 V/−0.9 V). Despite this, the proposed comparator operates sub-1 V supply voltages with input common mode voltage larger than 60% of supply voltage by utilizing a supply boosting technique. The measured power consumption of the supply boosted comparator for 1 V supply was 90 nW and speed was 6500 conversions per second, resulting in 14 pJ per conversion energy efficiency.
Highlights
Comparators are one of the fundamental building blocks affecting key performance parameters of mixed-signal subsystems such as analog-to-digital converters (ADCs)
A test setup shown in Figure 6 was developed for measuring static and dynamic characteristics of the supply boosted comparator (SBC)
It was shown that supply boosting technique (SBT) improves the common mode input range of the comparator, achieving both high precision and low energy operation
Summary
Comparators are one of the fundamental building blocks affecting key performance parameters of mixed-signal subsystems such as analog-to-digital converters (ADCs). To achieve low ripple, sophisticated charge pump circuits have to be used which increase circuit complexity, size, and power consumption Another important design requirement is that the boosted supply voltage has to be less than the maximum allowed process supply voltage (VAAP) for reliable device operation due to increased internal electric field. It generates boosted supply and reset signal employing a one-shot charge pump circuit [16]. The supply boosted level shifter circuit is composed of p-type source followers driving and isolating input nodes from supply boosted comparator core Voltage of the second LC is not boosted so that the logic level is restored before being driven by the inverter buffers which have high switching thresholds
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