Energy-Efficient Hardware Architectures for Fast Polar Decoders

Abstract

Interest in polar codes has increased significantly upon their selection as a coding scheme for the 5th generation wireless communication standard (5G). While the research on polar code decoders mostly targets improved throughput, few implementations address energy consumption, which is critical for platforms that prioritize energy efficiency, such as massive machine-type communications (mMTC). In this work, we first propose a novel Fast-SSC decoder architecture that has novel architectural optimizations to reduce area, power, and energy consumption. Then, we extend our work to an energy-efficient implementation of the fast SC-Flip (SCF) decoder. We show that sorting a limited number of indices for extra decoding attempts is sufficient to practically match the performance of SCF, which enables employing a low-complexity sorter architecture. To our knowledge, the proposed SCF architecture is the first hardware realization of fast SCF decoding. Synthesis results targeting TSMC 65nm CMOS technology show that the proposed Fast-SSC decoder architecture is 18% more energy-efficient, has 14% less area and 30% less power consumption compared to state-of-the-art decoders in the literature. Compared to the state-of-the-art available SC-List (SCL) decoders that have equivalent error-correction performance, proposed Fast-SCF decoder is 29% faster while being $2.7\times $ more energy-efficient and 51% more area-efficient.