Energy Efficient Hardware Architecture for Matrix Multiplication

Abstract

Matrix Multiplication features in many engineering and scientific problems, the reason which working on efficient algorithms and architectures to perform matrix multiplication is still relevant. In this work, we bring forward an efficient algorithm that is targeted towards the hardware implementation for generating a matrix multiplier targeted according to the input parameters of the user. The proposed architecture utilizes a carry-save adder tree multiplier for multiplication and carry-lookahead adder for performing addition at the final stage. When compared with state-of-the-art matrix multiplication algorithms like Strassen and Winograd, our architecture achieves a better energy efficiency of 59% and 69% respectively, and area delay product (cycle budget) of 58% and 73% respectively. The proposed architecture is well suited for power critical applications with a negligible impact on the delay.