Energy efficient design and implementation of ALU on 40nm FPGA

Abstract

There is 67.04% dynamic power reduction with LVCMOS12 when we migrate from 90-nm Spartan-3 FPGA to 40-nm Virtex-6 FPGA. There is 81.19%, 92.05% dynamic power reduction when using LVCMOS12 in place of HSTL_II_18 and SSTL2_I_DCI respectively. We achieved 65.56%, 72.59% and 73.41% dynamic power reduction in ALU with LVDCI IO standard in place of LVDCI_DV2, HSTL_I, and LVCMOS12 respectively. There is 68.34% and 52.51% dynamic power reduction in ALU when using LVCMOS12 and LVCMOS15 in place of LVCMOS25. There is 62.45% dynamic power reduction in ALU, when we use HSTL_I in place of SSTL2_I_DCI. Power is directly proportional to frequency. With increase in frequency, there is increase in power consumption irrespective of IO standard. LVCMOS is the only IO standard, which takes less power when we upgrade our design to latest FPGA.