Energy-Efficient and Calibration-Aware Fourier-Domain OCT Imaging Processor

Abstract

This paper presents a novel Fourier-domain optical coherence tomography (FDOCT) imaging processor capable of performing all image formation operations, including dc removal, resampling, real-valued fast Fourier transform (RFFT), and display rendering. Optimizing an RFFT unit through complex-valued FFT computation makes it possible to reduce the clock rate required for the RFFT and post-RFFT units by half, thereby enhancing energy efficiency. A novel resource-sharing scheme further enables calibration (i.e., calculation of resampling indices) awareness checking with minimal area overhead. This makes the proposed FDOCT imaging processor ideally suited to portable OCT application. A test chip operating at dual 80/40 MHz was designed using the Taiwan Semiconductor Manufacturing Company 0.18- $\mu \text{m}$ technology. In postlayout simulation of FDOCT imaging mode, the test chip was shown to consume only 283.6 mW, which represents a power saving of 29% compared to an equivalent design without optimization. The proposed design was also verified at the system level using a field programmable gate arrays (FPGA) platform. In evaluation experiments, we could achieve 78-KHz A-line scan and 30-fps $512\times 1000$ OCT image display. The developed FPGA design also supports calibration awareness check using modest hardware resources.