Energy dissipation and constitutive modeling for a mechanistic description of pad scratching in chemical–mechanical planarization

David C Ponte,D M L Meyer

doi:10.1007/s10854-015-3949-4

Abstract

A thermomechanical model to describe the mechanisms of polishing pad scratching in chemical–mechanical planarization (CMP) has been formulated and investigated. CMP is a necessary process in integrated circuit (IC) fabrication to planarize wafers with nanoscale features after patterned layer deposition. Polishing pad asperities can produce microscale scratches on the wafer surface during CMP, reducing IC manufacturing yields. The constructed thermomechanical model accounts for stresses of the pad and wafer contact and also provides the means to track input energy dissipation during CMP. Tracking energy dissipation offers information about processes that may influence scratch production. This knowledge ultimately produces a greater physical understanding of CMP for the prevention of pad scratching. Polishing pad stress relaxation experiments demonstrate the importance of viscoelastic and plastic strain energy dissipation with its effects on the wafer stress field. Scratch producing ability of the polishing pad is found to decrease with use in CMP, with slurry soaking and increasing polishing time. Mechanical behavior of the polishing pad is demonstrated to differ when in compression and in tension. Compressibility of the pad material is shown to be significant in stress modeling through experimental measurement of polishing pad volume change. Differential scanning calorimetry of used polishing pad samples revealed energy dissipation into the polishing pad surface with increasing polishing time of CMP. Energy dissipation processes influence pad scratching in CMP. Analytical wafer stress field modeling unveils that the scratching ability of a polishing pad decreases when it is less stiff or has a smoother surface.

Highlights

Chemical-mechanical planarization (CMP) is a necessary step in the fabrication of state-of-the-art integrated circuits (ICs)
A thermomechanical model of the scratching process is formulated to account for the input energy that is dissipated through the pad scratching process
The ability for the pad to scratch the wafer decreases with pad use, since the coefficient of friction decreases the stress on the wafer surface

Summary

Introduction

Chemical-mechanical planarization (CMP) is a necessary step in the fabrication of state-of-the-art integrated circuits (ICs). With a process that requires accuracy and precision to the nanoscale, CMP is a challenging process to achieve high manufacturing yields. It has only recently been reported in the literature that IC wafer defects can be produced from the polishing pad material itself [1]. Soft polishing pads can induce scratches on harder wafers that are large enough to greatly reduce manufacturing yields. Previous work investigating CMP pad scratching provides mechanical criteria based on contact mechanics which can predict scratching and presents methods to reduce damage [1,2,3]. Experimental results from this work indicated that not all pad scratches are eliminated from CMP with one or more of these criteria

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Conclusion