Abstract
All-spin logic (ASL) is a spin-based candidate for implementing logic in the next generation designs. The energy and the delay of ASL circuits are both inherently related to the geometric parameters of ASL gates, and the careful selection of the dimensions for ASL gates is required to achieve optimal performance. In this paper, a tradeoff relation between the energy and the delay is explored to optimally size the magnets and channels in an ASL gate to provide an optimal balance under various delay and energy demands. Results on optimizing interconnects and benchmark circuits are presented.
Highlights
S PIN-BASED computing is a post-CMOS technology candidate that has recently seen an increased research focus
We study the methods for improving the performance of All-spin logic (ASL) circuits through the careful selection of the dimensions of circuit elements, resulting in energy–delay tradeoffs
We show that for the buffer chain, the total delay and the energy consumption of the ASL circuit are both posynomial functions, which implies that the optimization problem is a posynomial program [15] that can be solved to find the length of each magnet as well as the interconnect length in each stage
Summary
S PIN-BASED computing is a post-CMOS technology candidate that has recently seen an increased research focus. B. ANALYTICAL MODEL FOR SWITCHING DELAY IN ASL CIRCUITS For the gate, annotated with its geometrical parameters, we consider each contributor to switching: spin current generation at the input, nonlocal spin transport through the channel, and spin-torque-based switching at the output. The charge current at the input magnet is transformed into a spin current at the source end, which drifts down toward an output magnet through a lossy interconnect medium We capture these factors and arrive at an expression for the input–output delay of an ASL gate. For such structures, there is no known simple analytical form for the spin current, analogous to (3), at the output magnet(s). As in the static timing analysis for CMOS circuits, once the delays of each logic stage (i.e., a gate and its fan-out interconnect) are computed using the techniques described earlier a topological traversal from the primary inputs to the primary outputs can be used to find the delay of the circuit
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