Energy- and area-efficient parameterized lifting-based 2-D DWT architecture on FPGA

Abstract

State-of-the-art DWT designs focus on improving hardware utilization and memory efficiency of DWT. In this paper, we consider energy efficiency as the key performance metric. Memory (external memory and on-chip memory) energy dominates the total energy consumption. We propose a DWT architecture with an overlapped block-based image scanning method that optimizes the number of external memory accesses and the on-chip memory size. Using the overlapped block-based scanning method, the required number of external memory accesses of the proposed architecture is reduced by up to 50% when compared with state-of-the-art designs. Besides, the on-chip memory size is also reduced. We implement the proposed architecture on a state-of-the-art FPGA for various image sizes. Our design sustains up to 80.2% of the peak energy efficiency of the device. Compared with the state-of-the-art design, the proposed architecture achieves up to 58.1% energy efficiency improvement.