Energy- and Area-Efficient Spin–Orbit Torque Nonvolatile Flip-Flop for Power Gating Architecture

Abstract

This paper proposes two enhanced architectures for spin–orbit torque nonvolatile flip-flop (SOT-NVFF), namely, parallel programming scheme (pSOT-NVFF) and series programming scheme (sSOT-NVFF). At given SOT magnetic tunnel junction (SOT-MTJ) technology, the pSOT-NVFF achieves 29% lower backup energy with nearly 50% shorter backup delay compared with previous parallel architectures and the sSOT-NVFF offers at least 42% lower backup energy with 52% higher speed compared with others. Further analysis of the two proposed architectures showed a preferred window of operation for each architecture as a function of heavy metal electrode resistance ( $\text{R}_{HM}$ ). In particular, sSOT-NVFF is preferred, from speed and energy perspectives, for SOT-MTJs with small $\text{R}_{HM}$ (i.e., hundreds of $\Omega $ to tens of $\text{k}\Omega$ ), while pSOT-NVFF is preferred for SOT-MTJs with large $\text{R}_{HM}$ in the range of hundreds of $\text{k}\Omega $ . Further study indicates that our NVFF is robust, stable, and functional even with process variations.