Endurance of thin-oxide nonvolatile MNOS memory transistors

Abstract

A discussion of the factors which determine the endurance of thin-oxide MNOS Memory Transistors. Si-SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> Interface States are influential in the early stages of erase/write cycling, while charge movement into the nitride controls the long term cycling characteristics. The preparation of the thin-oxide region, its composition, dielectric properties and thickness; a high density of spatially localized traps near the nitride/oxide interface; a low conductivity Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</inf> dielectric; and optimized electric field strengths permit MNOS Memory Transistors to be operated with high endurance, reliably to beyond 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> erase/write cycles with ± 20v, 100µsec pulses and demonstrate a minimum 2v memory window at 6 months retention time.