ENCHANCED LINKED-BASED CACHE COHERENCE PROTOCOLS WITH A HARDWARE MECHANISM TO REDUCE THE MIGRATORY SHARING OVERHEAD

Abstract

The linked-based cache coherence protocols, such as the IEEE Scalable Coherence Interface (SCI), have been widely implemented in current highly scalable multiprocessor systems. Thus, we propose several enhanced linked-based cache coherence protocols in multiprocessor systems to evaluate their performance. However, migratory sharing data references in the linked-based systems still incur many cache misses that can be reduced by merging the invalidation/update requests and the cache misses. Research has been devoted to optimizing the migratory sharing references for the centralized directory coherence protocols, but their mechanisms cannot support the linked-based cache coherence protocols. This paper presents enhanced SCI protocols with an effective hardware technique to reduce the overhead of migratory sharing references for the linked-based cache coherence protocols. It reduces cost by eliminating some of the unnecessary supporting mechanisms in centralized directory protocols. The simulation results in SPLASH benchmarks show that our hardware methods enhanced the system performance by up to an average of 10%, by reducing the overhead of the migratory sharing references. The extra benefit of our mechanism is the elimination of the false sharing overhead by degrading a block to shared mode again.