Enabling Wafer Level Processes for CIS Manufacturing

Abstract

CMOS (Complimentary Metal Oxide Semiconductor) Image Sensors have become ubiquitous, appearing in cars, cell phones, toys and many other devices used in every day life. The primary reason for this increasing presence of CIS (CMOS Image Sensors) is the continual improvement of the performance to cost ratio of these devices. The drivers behind this are the advancements of CMOS image sensor technology such as improved signal to noise ratio as well as advancements in wafer level processing technology related to 3D packaging. Numerous process developments related to both the electrical and optical aspects of 3D packaging of CIS that have enabled this climb up the performance vs. cost curve will be reviewed in this paper with particular attention to:(1) Lens molding – The ability to mold lenses, both spherical and aspherical at the wafer level as well as make full size master stamps from partial masters for lens molding. These lenses can be molded on both sides of a wafer and the lenses aligned to each other;(2) Aligned wafer bonding for optical interconnects consisting of lens stacks and CIS wafer, to allow the thinning of a CIS for BSI (back side illumination), and for electrical interconnects. Together these processes allow the heterogeneous integration of optical and electrical elements at the wafer level and advance the CIS up the performance vs. cost curve.