Enabling High-Rate Plating in Solid-State Li Batteries By Interface Engineering and Pulse Plating

Abstract

High power solid-state Li batteries (SSLB) are hindered by the formation of dendritic structures at high current rates. One of the main reasons for their formation are current constriction that arise from inhomogeneous electrical field distributions at the Li metal | solid-electrolyte interface that originates from, e.g., (i) poor contact between Li metal and the solid electrolyte or (ii) the Li metal void formation during Li metal stripping.1,2 Herein, we present a solution achieved via thorough sample preparation consisting of a mixture of polishing steps, heat treatments and the usage of a molten lithium alloy to effectively wet the electrolyte. This reduces the interfacial resistance to negligible values, which enables critical current density (CCD) up to 4 mA/cm². Moreover, we applied different current waveforms (i.e., pulse plating) to homogenize the current distribution at the interface, which increases the CCD significantly to a value of up to 6.3 mA/cm². These results, suggest that the combination of interface engineering in combination with alternative current waveforms are promising strategies to reach the power requirement for future electrical vehicles.