Abstract
Many high energy physics experiments based their serial links on the Agilent HDMP-1032/34A serializer/deserializer chip-set (or GLink). This success was mainly due to the fact that this pair of chips was able to transfer data at ~ 1 Gb/s with a deterministic latency, fixed after each power up or reset of the link. Despite this unique timing feature, Agilent discontinued the production and no compatible commercial off-the-shelf chip-sets are available. The ATLAS Level-1 Muon trigger includes some serial links based on GLink in order to transfer data from the detector to the counting room. The transmission side of the links will not be upgraded, however a replacement for the receivers in the counting room in case of failures is needed. In this paper, we present a solution to replace GLink transmitters and/or receivers. Our design is based on the gigabit serial IO (GTP) embedded in a Xilinx Virtex 5 Field Programmable Gate Array (FPGA). We present the architecture and we discuss parameters of the implementation such as latency and resource occupation. We compare the GLink chip-set and the GTP-based emulator in terms of latency, eye diagram and power dissipation.
Highlights
T RIGGER systems of High Energy Physics (HEP) experiments need data transfers to be executed with fixed latency, in order to preserve the timing information
In order to test our link, we deployed two off-the-shelf boards [19] built around a Virtex 5 LX50T Field Programmable Gate Array (FPGA)
SerDes embedded in FPGAs have a lower power dissipation with respect to external SerDes chip-sets and their datarates and transmission protocols can be changed by re-programming the FPGA
Summary
T RIGGER systems of High Energy Physics (HEP) experiments need data transfers to be executed with fixed latency, in order to preserve the timing information. This requirement is not necessarily satisfied by Serializer-Deserializer (SerDes) chip-sets. The HighpT PAD box can send triggers and data from the detectors (and from the Low-pT PAD box) to a off-detector VME board, the Sector Logic/RX (SL/RX) [13], via an 800-Mbps serial link based on the GLink chip-set. Each SL/RX board includes 8 GLink receivers and two FPGAs handling the received data and the communication with other off-detector boards: the Read Out Driver (ROD) [14] and the Muon Central Trigger Processor Interface (μCTPI). Data are eventually transferred to the Read Out System for further elaborations or storage
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