Emulating Switching From Short-Term to Long-Term Plasticity of Bio-Synapse Using Split Gate MOSFET

Abstract

For the development of brain-inspired neuromorphic hardware with high integration density and connectivity in this work, we have proposed a fully planar, CMOS compatible, and energy efficient (inference energy &#x003D; 7.4x10^-17 J) tunable-split gate synaptic transistor (T-SGST) with correlation-based plasticity. Valence band offset (VBO) in the device due to SiGe region and charge trapping&#x002F;de-trapping in the nitride layer are found to be effective for synaptic learning (short-term potentiation (STP), long-term potentiation (LTP), and long-term depression (LTD)) at low trapping&#x002F;de-trapping voltage (<inline-formula><tex-math notation="LaTeX">${V}_{G2S} = | {3.5} |V$</tex-math></inline-formula>). Furthermore, the switching from STP to LTP is governed by repeated input pulses (correlation-based plasticity) and the bias potential on gate 1 (G1). The proposed T-SGST offers a switching at the 8^th input pulse when G1 is tuned at <i>V_G</i>₁<i>_S</i> &#x003D; 0 V, whereas for <i>V_G</i>₁<i>_S</i> &#x003D; -0.2 V there is no switching. In addition, we have also reported the strong dependence of the interval time between input pulses on switching. These findings in our proposed T-SGST device make it a promising candidate for application in the neuromorphic technology.