Empowering Mixed-Criticality System Engineers in the Dark Silicon Era: Towards Power and Temperature Analysis of Heterogeneous MPSoCs at System Level

Abstract

With the predicted device, core, and multi-core scaling, a recent study revealed that regardless of chip organization and topology, multi-core scaling is power limited. It has been predicted that at 22 nm, 21 % of a fixed-size chip must be powered off, and at 8 nm, even more than 50 % (Esmaeilzadeh et al., News 39(3):365–376, 2011). Especially for mixed-criticality systems, which consist of a mixture of safety and non-safety relevant applications, this is of major concern. Safety-critical applications cannot be simply switched on and off or migrated during run-time. A system engineer should be aware of any possible cross-application interferences with respect to timing, power, and thermal properties as soon as possible in the design process. Introduction of power and temperature management must be planned and realized without violating freedom from interference. For this reason, the extra-functional properties need to be modeled and analyzed at the system level, because they can strongly affect the overall quality of service (performance, battery lifetime) or even cause the system to fail meeting its real-time and safety requirements.In this chapter, we present our vision of a SystemC-based simulation framework for capturing extra-functional properties in virtual platforms, currently under development in the CONTREX project. This covers the specification of platform properties (extra-functional model) as well as the dynamic capturing, processing, and extraction of power/temperature information during the simulation. Especially closing the loop back to the application and run-time services is an important feature for complex heterogeneous hardware platforms and software stacks. As an example, we will present a battery-powered mixed-critical avionics system, running a safety-critical flight control application and a performance critical image processing application on the same multi-core System on Chip.