Empirical Study of the Cut-Off Frequency of Multi-Finger Nanometer MOS Transistor

Numerical analysis of the cut-off frequency of ultra-small ballistic double-gate MOSFETs: 2D nonequilibrium Green’s function approach

In this paper, the radio-frequency (RF) performances and small-signal parameters of double-gate (DG) square-shaped extended source tunneling field-effect transistors (TFETs) are investigated and compared with those of single-gate (SG) square-shaped extended source TFETs in terms of their cut-off and maximum oscillation frequencies and small-signal parameters. By using of a nonquasi-static (NQS) radio-frequency model, the small-signal parameters have been extracted. The results show that the DG square-shaped extended source TFET has higher transconductance, cut-off and maximum oscillation frequencies than single gate structure. The modeled Y-parameters are in close agreement with the extracted parameters for high frequency range up to the cut-off frequency. Results suggest that the DG square-shaped extended source TFETs seem to be the most optimal ones to replace MOSFET for ultralow power applications and RF devices.

<p>This study reviews related studies on the impact of the layout dependent effects on high frequency and RF noise parameter performances, carried out over the past decade. It specifically focuses on the doughnut and multi- finger layouts. The doughnut style involves the polygonal and the 4- sided techniques, while the multi-finger involving the narrow-oxide diffusion (OD) and multi-OD. The polygonal versus 4-sided doughnut, and the narrow-OD with multi-fingers versus multi-OD with multi- fingers are reviewed in this study. The high frequency parameters, which are of concern in this study, are the cut- off frequency (f<sub>T</sub>) and the maximum frequency (f<sub>MAX</sub>), whereas the noise parameters involved are noise resistance (R<sub>N</sub>) and the minimum noise figure (NF<sub>min</sub>). In addition, MOSFET parameters, which are affected by the layout style that in turn may contribute to the changes in these high frequency, and noise parameters are also detailed. Such parameters include transconductance (G<sub>m</sub>); gate resistance (R<sub>g</sub>); effective mobility (μ<sub>eff</sub>); and parasitic capacitances (c<sub>gg</sub> and c<sub>gd</sub>). Investigation by others has revealed that the polygonal doughnut may have a larger total area in comparison with the 4- sided doughnut. It is also found by means of this review that the multi-finger layout style with narrow-OD and high number of fingers may have the best performance in f<sub>T</sub> and f<sub>MAX</sub>, owing partly to the improvement in G<sub>m</sub>, μ<sub>eff</sub>, c<sub>gg</sub>, c<sub>gd</sub> and low frequency noise (LFN). A multi-OD with a lower number of fingers may lead to a lower performance in f<sub>T</sub> due to a lower G<sub>m</sub>. Upon comparing the doughnut and the multi-finger layout styles, the doughnuts appeared to perform better than a standard multi-finger layout for f<sub>T</sub>, f<sub>MAX</sub>, G<sub>m</sub> and μ<sub>eff</sub> but are poorer in terms of LFN. It can then be concluded that the narrow-OD multi-finger may cause the increase of c<sub>gg</sub> as the transistor becomes narrower, whereas a multi-OD multi-finger may have high R<sub>g</sub> and therefore may lead to the increase of f<sub>T</sub> and f<sub>MAX</sub> as the transistor becomes narrower. Besides, the doughnut layout style has a higher G<sub>m</sub> and f<sub>T</sub>, leading to larger μ<sub>eff</sub> from the elimination of shallow trench isolation (STI) stress.</p>

Influence of multi-finger layout on the subthreshold behavior of nanometer MOS transistors

The dc and RF analog characteristics of ultrathin gate oxide CMOS on [110] surface-oriented Si substrates were investigated for the first time. The transconductance of p-MOSFETs on [110] substrates is 1.9 times greater than that on [100] substrates even in gate oxides in the direct-tunneling regime. An extremely high cutoff frequency of 110 GHz was obtained in 0.11 /spl mu/m gate length p-MOSFETs with 1.5 nm gate oxides. This is the highest value ever obtained for p-channel Si MOSFETs at room temperature. Further, it was demonstrated that more than 100 GHz of cutoff frequency is realized both for n- and p-MOSFETs. Thus, using [110] substrates results in a better balance for n- and p-MOS performances. The SiO/sub 2/ film and SiO/sub 2//Si interface qualities on [110] substrates were also investigated. In this experiment, it was found that direct-tunneling gate leakage current and initial 1/f noise of MOSFETs on [110] substrates are larger than those on [100] substrates. The reliability regarding Negative Bias Temperature Instability (NBTI) for p-MOSFETs on [110] substrates was also inferior to that for [100] MOSFETs. However, with a high-k insulator or improvement of the SiO/sub 2/ film quality, high mobility of p-MOSFETs on [110] substrates will have a potential not only for digital applications but also for new RF analog circuits under low supply voltage.

Investigation on holding voltage of asymmetric DDSCR with floating heavy doping in 0.18 μm CMOS process

Normally-off p-gallium nitride (GaN) high electron mobility transistor (HEMT) devices with multi-finger layout were successfully fabricated by use of a self-terminating etching technique with Cl2/BCl3/SF6-mixed gas plasma. This etching technique features accurate etching depth control and low surface plasma damage. Several devices with different gate widths and number of fingers were fabricated to investigate the effect on output current density. We then realized a high current enhancement-mode p-GaN HEMT device with a total gate width of 60 mm that exhibits a threshold voltage of 2.2 V and high drain current of 6.7 A.

The influence of the noise figure on both gate and drain source voltage, threshold voltage and transistor size have been investigated for the design of low noise integrated circuits. Therefore, a device model for both high frequency small signal and noise behavior of InP-HEMTs, depending on both gate and drain voltage, has been developed. It was found that the lowest noise is observed when the drain current for maximum gain is reduced to a third while the drain voltage is reduced to the start of the saturation region V/sub ds/=0.6 V. However, it was shown for the first time that the bias for lowest noise is frequency dependent. Modeling scaling effects of the noise behavior shows, that lowest noise is observed for a gate width of 1/spl times/40 /spl mu/m. Multi-finger layouts are preferable for gate widths above 70 /spl mu/m. Furthermore, it is shown that the optimum width of each finger decreases with the number of fingers.

A practical device model for both high frequency small signal and noise behavior of InP-HEMT's depending on both gate and drain voltage has been developed. The model is based on the two-piece linear approximation using charge control and saturation velocity models. Combining large signal model and analytical expressions for the noise source parameter P, R, and C, an analytical bias-dependent noise model can be obtained. For implementation into high frequency simulation software, the exact calculated bias dependence was mathematically fitted by elementary functions. It could be shown that lowest noise is observed when the drain current for maximum gain is reduced to a third while the drain voltage is reduced to the start of the saturation region V/sub ds/=0.6 V. Modeling scaling effects of the noise behavior shows that lowest noise is observed for a gate width of 1/spl times/40 /spl mu/m. Multi-finger layouts are preferable for gate widths above 70 /spl mu/m. Furthermore it is shown, that the optimum width of each finger decreases with the number of fingers.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Metal-insulator-semiconductor field effect transistors (MISFETs) using low temperature (LT) GaAs as the insulator layer were fabricated and characterized. In this study, the influence of the AlAs spacer layer on MISFET properties is explored. Structures were grown with the thickness of the AlAs layer varied from 0 to 30 nm with the remainder of the total 60 nm insulator layer composed of LT GaAs. Two control structures were also grown, a standard metal semiconductor field effect transistor (MESFET) and a MISFET with a 50 nm Al/sub 0.80/Ga/sub 0.20/As insulator layer. Transistors with 1.2*200 mu m gates and 5 mu m source drain spacings were fabricated using standard processing techniques. Breakdown voltages as high as 48 V were found for the LT MISFETs, compared to 5 V for the MESFET and 12 V for the Al/sub 0.80/Ga/sub 0.20/As MISFET. The detailed characterization of the breakdown, along with the effects of the various insulating layers on other FET parameters such as current, transconductance, and cutoff frequency, is described. >

Nanoscale complementary metal–oxide–semiconductor (CMOS) circuit design extensively employs multifinger layout technique to alleviate the performance degrading parasitic and mismatch effects that are typically observed with single-finger layout. However, a continuous increase in the number of fingers accompanied by a simultaneous decrease in their finger width could lead to the penalty of a higher degree of variation in the MOSFET's small-signal parameters. It is due to the heightened shallow trench isolation (STI) stress that gets developed in such devices. The optimisation of circuit performance with the arbitrarily fixed number and width of fingers would be ambiguous. In this work, an analysis of current–voltage (I–V) characteristics of a MOSFET as a function of number of fingers has been proposed. It was found that both the drain current and gate transconductance get affected by the number of fingers. The authors proposed a Miller-compensated two-stage [operational transconductance amplifier (OTA)] and common source amplifier by considering STI effect. It is also found that the parameters of the proposed design matched well with the set of desired specifications. Also, the area of multifinger MOSFET OTA is lowered by up to 60% relative to that from the conventional. All post-layout simulations were performed using standard UMC 65 nm CMOS technology.

This paper presents a study on the effects of different layout methods on the noise performance of RF CMOS transistors. The optimization of RF characteristics using multifinger layout and a more compact waffle layout with Manhattan-oriented polysilicon gate are studied. The waffle layout is demonstrated to have a larger design window through the simulation as well as the experimental data. The improvement of both the maximum oscillation frequency f/sub max/ and the cutoff frequency f/sub T/ at the same biasing condition leads to the improvement on RF noise performance for the waffle MOSFETs. Compared with the multifinger devices, the SpectreRF simulation reveals that 10% reduction in noise figure is achieved when the waffle MOSFETs are used in CMOS low-noise amplifiers.

We investigate the effects of the number of gate fingers (N) and gate width (W) on the high-frequency characteristics of 0.1 µm depletion-mode metamorphic high-electron-mobility transistors (MHEMTs). The extracted gate-to-source capacitance (Cgs), gate-to-drain capacitance (Cgd), intrinsic transconductance (gm,int), and drain conductance (Gds) are proportional to total gate width (wt), whereas intrinsic resistance (Ri) and source resistance (Rs) are inversely proportional to wt. Gate resistance (Rg) linearly increases at various slopes with non-zero gate resistances at zero gate width depending on N. The cutoff frequency ( fT) and maximum frequency of oscillation ( fmax) are calculated using a small-signal model and curve-fitting equations extracted from each small-signal parameter. fT is almost constant; however, fmax is a strong function of Rg1/2 and is affected by both N and wt. A large wt produces a low fmax; however, at a given wt, increasing the number of gate fingers is more efficient than increasing single gate width for maximizing the fmax.

An AlGaAs/InGaAs/GaAs pseudomorphic metal-insulator-semiconductor field-effect transistor (MISFET) was investigated both in FET- and charge-injection transistor (CHINT)-mode operation. It is demonstrated that a CHINT-mode operation and a large negative differential resistance as well as good FET characteristics can be obtained in MISFETs with a very thin gate barrier layer. Furthermore, the cutoff frequency in CHINT mode-operation was 32 GHz for a MISFET with a gate length of 1 µm. This is about twice as large as that obtained in FET-mode operation. The equivalent circuit analysis revealed that the output conductance and the source resistance play an important role in determining the cutoff frequency, in contrast to ordinary FETs. The intrinsic cutoff frequency (Rs=0) was as large as 57 GHz.

Abstract: This letter is the study on impact of source/drain engineering on Single Gate (SG) and Dual Gate (DG) Junctionless MOSFET. Both the proposed MOSFET have Gate Stacking and highly doped source/drain region, so name suggested is Highly Doped Source Drain Gate Stack Junctionless (HDSD-GSJL) MOSFET. Here we investigate the effect of highly doped source/drain, gate stacking and double gate on junctionless MOSFET. The investigation is performed in relations of Analog and RF figure of merits (FOMs). In the paper major FOMs, output conductance (gd), Transconductance Frequency Product (TFP), cut-off frequency (fT) and transconductance (gm) is analyzed. The result shows that Double Gate HDSD-GSJL MOSFET exhibit high gm, high ft and high TFP. The structure is analyzed and designed using ATLAS 2D TCAD tools. Keywords: HDSD-GSJL, SG, DG, Analog and RF FOMs Cite this Article Jyotsana Singh, Narendra Yadava, R.K. Chauhan. Impact of Source/Drain Engineering on Performance of Single Gate and Dual Gate Junctionless MOSFET. Journal of Semiconductor Devices and Circuits 2019; 6(1): 10–14p.