Empirical model of data retention degradation in stacked-gate flash EEPROM cells with new interpoly dielectric of an Oxide–Nitride–Oxide–Nitride (ONON) layer

Abstract

We have studied the reliability problems in the degradation of the data retention characteristics of the stacked-gate flash EEPROM devices with the new interpoly dielectric of an Oxide–Nitride–Oxide–Nitride (ONON) layer instead of a conventional Oxide–Nitride–Oxide (ONO) layer. Based on the experimental results of cell threshold voltage shifts measured as a function of bake time at various temperatures by the high-temperature accelerated test, an empirical model equation has been developed and evaluated, which explains the dominant mechanisms for the spontaneous electron leakage through the interpoly dielectric. Through the threshold voltage and temperature dependency of cell threshold voltage shift rate, the model clearly shows that cell threshold voltage shift during the baking test is caused dominantly by the electron leakage mechanism due to the thermally-activated direct-tunneling which electrons tunnel finally through the thin top oxide of the ONON layer to the control gate after detrapping the internitride trap-sites near the interface between the internitride and top oxide by the thermionic emission mechanism. The simulation results using the model equation were quite consistent with the measurement data at all the tested temperatures and times.