Abstract
Information about the distribution of path-lengths in a Binary Decision Diagrams (BDDs) representing Boolean functions is useful in determining the speed of hardware and software implementations of the circuit represented by these Boolean functions. This study presents expressions produced from an empirical analysis of a representative collection of Boolean functions. The Average Path Length (APL) and the Shortest Path Length (SPL) have simple behavior as function of the number of variables and the number of terms used in the construction of the Sum of Products (SOPs) in Boolean expressions. We present a generic expression that is uniformly adaptable to each curve of path-length versus number of terms over all the empirical data. This expression makes it possible to estimate the performance characteristics of a circuit without building its BDD. This approach applies to any number of variables, number of terms, or variable ordering method.
Highlights
The use of logic verification and optimization algorithms in VLSI CAD systems requires efficient representation and manipulation of Boolean functions[1]
Over the past two decades most of the problems in the synthesis, design and testing of combinational circuits, have been solved using various mathematical methods[5,6]. Researchers in this area are actively involved in developing mathematical models that predict the number of nodes in a Binary Decision Diagrams (BDDs) in order to predict the complexity of the design in terms of the time needed to optimize it and verify its logic
We are in the process of investigating an automated global fit for any Shortest Path Length (SPL) and Average Path Length (APL) curves in order to find the complexity for any number of product terms
Summary
The use of logic verification and optimization algorithms in VLSI CAD systems requires efficient representation and manipulation of Boolean functions[1]. Over the past two decades most of the problems in the synthesis, design and testing of combinational circuits, have been solved using various mathematical methods[5,6] Researchers in this area are actively involved in developing mathematical models that predict the number of nodes in a BDD in order to predict the complexity of the design in terms of the time needed to optimize it and verify its logic. In this example we will compute the APL and the SPL: Relation between the size of a boolean function and the ROBDD complexity[20]: The complexity of the ROBDD mainly depends on the number of nodes represented by the ROBDD. The APL and SPL reaches a maximum ( APL ≅ 7.73 , SPL ≅ 5.4 in this case)
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