EMI Mitigation with Stacking DBC Substrate for High Voltage Power Module

Abstract

The fast switching speed of high voltage silicon carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) can achieve high power density but are accompanied by significant common-mode (CM) current. The CM current propagates through the parasitic capacitor between the floating electrical potential and the grounded baseplate, which leads to conduct electromagnetic interference (EMI) noise. This paper focuses on the CM EMI mitigation in power module packaging. A 10kV/60A module configuration is proposed and optimized toward high insulation, low CM noise, and a convenient module-system interface. Stacking DBC substrates structure is utilized for the device-baseplate insulation, which provide a vertical structure for EMI shielding and paths for EMI mitigation. Furthermore, an extra pattern is etched on the middle layer of stacking DBC substrates for parasitic capacitance reduction. The EMI propagation loop difference between the conventional stacking DBC substrates and the proposed structure with the middle layer pattern are compared. The optimized configuration and middle layer pattern offer a significantly reduced grounding capacitance by 37%.