Abstract
This chapter discusses the emerging field‐effect transistor (FET) architectures proposed to replace the conventional metal‐oxide‐ semiconductor field‐effect transistors (MOSFETs) in detail. It analyzes tunnel FETs (TFETs), impact ionization MOSFETs (I‐MOS), and ferroelectric FETs, which exhibit a sub‐60 mV/decade subthreshold swing. The chapter provides a discussion on the architectural design improvements such as two‐dimensional (2D) materials for channel, nanowires, and nanotube architectures to sustain the scaling of the conventional MOSFETs beyond the 10‐nm technology node. The TFETs work on the principle of interband tunneling. The nanowire FETs (NWFETs) may be fabricated using the popular bottom‐up techniques such as vapor‐liquid‐solid (VLS) growth, noncatalytic growth, solution‐processed growth, and suspended nanowire growth. Since a gate‐sidewall spacer is inevitable for realizing nanotube FETs (NTFETs), the spacer material may be used as an efficient tool for tuning the performance of the NTFETs.
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