Embedding Outerplanar Graphs in Small Books

Abstract

We investigate the problem of embedding graphs in books. A book is some number of half-planes (the pages of the book), which share a common line as boundary (the spine of the book). A book embedding of a graph embeds the vertices on the spine in some order and embeds each edge in some page so that in each page no two edges intersect. The pagenumber of a graph is the number of pages in a minimum-page embedding of the graph. The pagewidth of a book embedding is the maximum cutwidth of the embedding in any page. A practical application of book embeddings is in the realization of a fault-tolerant array of VLSI processors. Our result is an $O(n \log n)$ time algorithm for embedding an n-vertex outerplanar graph with small pagewidth. The algorithm embeds any d-valent outerplanar graph in a two-page book with $O(d\log n)$ pagewidth. This result is optimal in pagewidth to within a constant factor for the class of outerplanar graphs. As there are trivalent outerplanar graphs that require $\Omega (n)$ pagewidth in any one-page embedding, the pagenumber of our embedding is exactly optimal for the stated pagewidth. The significance for VLSI design is that any outerplanar graph can be implemented in small area in a fault-tolerant fashion.