Embedding Augmented Cubes into Grid Networks for Minimum Wirelength

Abstract

Deriving an effective VLSI layout for interconnected network is important, since it increases the cost-effectiveness of parallel architectures. Graph embedding is the key to solving the problems of parallel structure simulation and layout design of VLSI. Wirelength is a criterion measuring the quality for graph embedding. And it is extensively used for VLSI design. Owing to the limitation of the chip area, the total wirelength of embedded network becomes a key issue affecting the network-on-chip communication performance. \(AQ_{n}\), the n-dimensional augmented cube, is an important interconnection network topology proposed for parallel computers. In this paper, we first study the minimum wirelength of embedding augmented cube into a linear array based on the maximum induced subgraph problem. Furthermore, we obtain the exact wirelength of embedding augmented cubes into grids and propose a linear embedding algorithm to prepare for further study of efficient layout areas.