Embedded power-aware cycle by cycle variable speed processor

Abstract

A variable speed processor (VSP) that can adjust its clock period at each cycle, according to the instruction flow in a pipelined program, is presented. This allows performance enhancement and energy consumption reduction, which is an important consideration for the next generation of embedded processor designs. With little change to the standard synchronous design, speed can be enhanced without increasing energy or speed can be maintained with energy savings. The VSP concept is validated by coupling a Nios® processor with a variable period clock synthesiser (VPCS). No modifications to the core other than extracting internal signals from the pipeline are needed to control the VPCS. The VPCS cleanly switches between period lengths at each cycle, over a wide range of possible lengths and with any resolution depending on available clock phases. One VPCS design, in CMOS 0.18 µm, consumes less than 10 µW/MHz and is able to instantly switch inside the 4–250 MHz range. The VSP design is implemented with the Altera® Embedded System platform, in its Stratix® FPGA. With the proposed method, the dynamic energy consumed per program loop is reduced by 14%, while the processing time is reduced by 3.6% compared to the original standard Nios® processor running the same program at its maximum frequency (133 MHz).