Abstract
Recently in semiconductor memories such as embedded memories (SRAM, e-DRAM), main memories (DRAM) and storage memories (NAND memory), it is becoming difficult to meet the target performance only by scaling technologies. Especially for high speed embedded memories, the large power consumption brings more serious issues due to rapid increase in memory capacity under multi core MPUs, operation speed and leakage current of scaled CMOS. Moreover, the speed gap between each memory levels in addition to that between the operation speed of MPUs and that of embedded memories and main memories have expanded year by year.
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