Embedded FPGA Design for Optimal Pixel Adjustment Process of Image Steganography

Chiung-Wei Huang,Changmin Chou,Cheng-Yuan Chang,Yu-Che Chiu

doi:10.1155/2018/5216029

Abstract

We propose a prototype of field programmable gate array (FPGA) implementation for optimal pixel adjustment process (OPAP) algorithm of image steganography. In the proposed scheme, the cover image and the secret message are transmitted from a personal computer (PC) to an FPGA board using RS232 interface for hardware processing. We firstly embed k-bit secret message into each pixel of the cover image by the last-significant-bit (LSB) substitution method, followed by executing associated OPAP calculations to construct a stego pixel. After all pixels of the cover image have been embedded, a stego image is created and transmitted from FPGA back to the PC and stored in the PC. Moreover, we have extended the basic pixel-wise structure to a parallel structure which can fully use the hardware devices to speed up the embedding process and embed several bits of secret message at the same time. Through parallel mechanism of the hardware based design, the data hiding process can be completed in few clock cycles to produce steganography outcome. Experimental results show the effectiveness and correctness of the proposed scheme.

Highlights

In this digitized era, almost all kinds of information such as plain texts, voices, images, and videos can be digitally presented, leading to the birth of a wide range of digital media
The stego images produced by software implementation and by the proposed field programmable gate array (FPGA) implementation are shown in Figures 4(c) and 4(d), respectively
The secret messages extracted by software implementation and by the proposed FPGA implementation are shown in Figures 4(e) and 4(f), respectively

Summary

Introduction

Almost all kinds of information such as plain texts, voices, images, and videos can be digitally presented, leading to the birth of a wide range of digital media. The last-significant-bit (LSB) replacement method [8, 9], which proposes to replace the least k-bit of the cover images by the secret message, is the most straightforward algorithm for embedding message into images. FPGA supports sufficient logic arrays to implement more complicated systems and subsystems, and exploits the increasing capacity of integrated circuits to provide designers with reconfigurable logic arrays that can be programmed on application specific basis This drastically increases the flexibility in both the design process and the final manufacture by permitting a board-level design to perform many functions. The FPGA board, Xilinx Spartan-3E Starter Kit, is applied to fulfill the image data hiding technique Using both software and hardware based schemes, two image hiding experiments are fulfilled to compare the correctness and efficiency of the proposed hardware based FPGA method. Into images are presented to verify the enhancement of the hardware based image steganography technique

. Related Works

Experimental Results

Conclusions