Embedded Fault-Tolerant Accelerator Architecture for Synthetic-Aperture Radar Backprojection

Abstract

This paper presents an optimized multicore embedded architecture to speed up and improve the resilience of the execution of a backprojection algorithm targeting onboard synthetic-aperture radar (SAR) imaging systems for the space environment. The proposed architecture produces SAR images by computing approximations instead of the full precision of some arithmetic operations. The proposed solution was implemented on a Xilinx SoC device with a dual-core processor. The novel fault-tolerant system exhibits graceful degradation characteristics as it is able to produce images considered acceptable, that is, signal-to-noise ratio and on average with an SNR 0.65 dB less than the fault-free image, while providing a time reduction up to 33%, and a decrease up to 40% in energy consumption.