Abstract

Control system of HIRFL-CSR accelerator is now upgrading to new architecture based on Experimental Physics and Industrial Control System (EPICS), a control sub-system of High Voltage (HV) for slow extraction on CSRm must be redesigned with the new architecture. The hardware of the new system based on a high-performance FPGA controller. Researched on embedded EPICS technology and implemented core function of the sub-system based on the technology. This paper describes the design and implementation of the new control system.

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