Abstract
A novel data analysis technique for testing embedded ADCs known as data optimisation is presented that alleviates scan-path loading and, when used as part of a go/no-go test, reduces the amount of primary of primary-test data and computer-time intensive operations to a minimum. To implement this test technique, a BIST scheme is presented which increases the control and observation of an embedded ADC, and enables real-time testing of an embedded 8-bit ADC with a 78% reduction in the amount of data needed to be shifted off-chip. Finally, comparisons between theoretical, modelled and practical results are made and appropriate conclusions drawn.
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