Elimination of signal integrity problems of boundary scan circuit based on frequency domain transfer coefficient method

Abstract

Most designers do not pay much attention to the boundary scan circuit (BSC) design because of its relatively low operating frequency, typically in the range of 10 to 100MHz. However, with the advancement of transistor technology, the shorter transistor switching time makes signal integrity (SI) a critical design issue for multi-interconnect systems (MIS). This paper investigates the BSC in MIS from the SI perspective. A method based on Frequency Domain Transfer Coefficient (FDTC) is proposed to eliminate the SI problems during the early BSC design stage. The method analyzes SI problems of the boundary scan signals in frequency-domain and offers an insight of the root cause of the SI problems. With the method, the designers can avoid unnecessary design iterations to achieve optimal SI performance.