Electrothermal Large-Signal Model of III–V FETs Including Frequency Dispersion and Charge Conservation

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> An empirical large-signal III–V field-effect transistor (FET) model has been developed. Three improved drain-source current (<emphasis emphasistype="bold"><emphasis emphasistype="italic">I</emphasis></emphasis>–<emphasis emphasistype="bold"><emphasis emphasistype="italic">V</emphasis></emphasis>) modeling equations capable of representing arbitrarily shaped transconductance (<formula formulatype="inline"> <tex Notation="TeX">$G_m$</tex></formula>) curves are proposed from level-1 to level-3. These models are characterized by the static dc and the multibias pulsed <emphasis emphasistype="bold"><emphasis emphasistype="italic">I</emphasis></emphasis>–<emphasis emphasistype="bold"><emphasis emphasistype="italic">V</emphasis></emphasis> measurements along with their dependences on temperature, so as to account for the frequency dispersion and the self-heating effects. By partitioning the <formula formulatype="inline"> <tex Notation="TeX">$G_m$</tex></formula> plots into five regions, specific parameters of the various model levels can be directly associated with the regions. Besides, the fitting parameters have inherent consistent definitions among different model levels, where some of the key model parameters can be extracted directly from measurements. For the gate-charge formulation (<emphasis emphasistype="bold"><emphasis emphasistype="italic">Q</emphasis></emphasis>–<emphasis emphasistype="bold"><emphasis emphasistype="italic">V</emphasis></emphasis>), a novel charge-conservative gate charge model is presented to accurately trace the nonlinear gate–source (<formula formulatype="inline"><tex Notation="TeX">$C_{\rm gs}$</tex></formula>) and gate–drain (<formula formulatype="inline"> <tex Notation="TeX">$C_{\rm gd}$</tex></formula>) capacitance values. The comprehensive large-signal model is then validated by comparing the predicted <emphasis emphasistype="bold"><emphasis emphasistype="italic">I</emphasis></emphasis>–<emphasis emphasistype="bold"><emphasis emphasistype="italic">V</emphasis></emphasis>, <emphasis emphasistype="bold"><emphasis emphasistype="italic">C</emphasis></emphasis>–<emphasis emphasistype="bold"><emphasis emphasistype="italic">V</emphasis></emphasis>, <formula formulatype="inline"><tex Notation="TeX">$S$</tex></formula>-parameters as well as power characteristics with the measured results of III–V FETs. </para>