Abstract
High current simulation capability under electrostatic discharge (ESD) conditions for ESD self-protected front end module (FEM) switch applications in an RF SOI Technology is shown for the first time. A methodology showing how to adequately characterize CMOS switch devices under ESD conditions is reviewed. Additionally, a methodology for extraction of a high current compact wrapper model which includes the parasitic bipolar transistor placed in parallel with the base MOSFET compact model is shown. Successful compact model simulation to hardware correlation is shown under ESD stress events.
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