Electroplated copper nanowires as Thermal Interface Materials

Abstract

With the continued miniaturization of microelectronics and increased power densities, thermal management of electronic devices is a major challenge. One of the main bottlenecks in thermal management is the thermal contact resistance at the interfaces of the various device components. Typically, Thermal Interface Materials (TIMs) have been used to reduce the thermal contact resistance. An ideal TIM would have low thermal resistance to improve thermal performance as well as good mechanical compliance to reduce thermally-induced stresses due to the CTE mismatch between silicon and heatspreader or heatsink. In this paper, we build on previous work using copper nanowires as electrical interconnects and show that copper nanowire arrays can be easily fabricated and used as high-performance TIMs. High mechanical compliance is achieved due to the high aspect ratio structure of the array. The thermal resistance of the arrays is measured using an ASTM D5470 apparatus, and it is seen that the nanowire arrays have the potential of having a thermal resistance as low as 0.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> K/W.