Electroplated Copper for Heterogeneous Die Integration

Abstract

This paper introduces a heterogeneous die integration process using electroplated copper to mount a bare die into a silicon handling wafer while simultaneously forming vertical, through-wafer vias. Deep reactive-ion etching is used to form openings in the handling wafer allowing the die to be flush-mounted for minimal device thickness. The backsides of the support wafer and die are coated by copper sputtering and electroplating, which physically secures the die in place. Electrical isolation is achieved through passivation of the silicon handle wafer sidewalls before copper electroplating. Wet thermal oxide growth was chosen over plasma-enhanced chemical vapor deposition as the sidewall passivation technique, as wet thermal oxide was found to yield superior coverage and uniformity. Topside interconnects were realized using a previously established thick-film copper metallization process. A 3 × 3 die array was successfully produced and tested for die-to-die connectivity. Thermal modeling of the fabricated devices showed that power densities up to 1 W/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> could be accommodated while keeping the maximum temperature below 85°C.