Electron-volt, high current implants into silicon SDR (Surface damage region) and the effect of anneal time to form 200 to 700 angstrom, low leakage junctions

Abstract

As device geometry shrinks and the dimensions become very shallow the effect of the silicon surface becomes increasingly important. Normally shallow implant processes have been limited by Transient Enhanced Diffusion (TED). We have used a new technique with electron volt ion beams of B/sup +/ and As/sup +/ at high currents and new very fast spike annealing method. We show that the defect behaviour is strongly influenced by the proximity of the surface. Implants were performed with several milli-amperes in the energy range 200 eV to 1000 eV to introduce dopant close to the SiO/sub 2/ surface and activated with very short spike anneals to achieve high conductivity, low leakage, low capacitance junctions suitable for Gigabit DRAM and ultra-fast logic applications. We used Spreading Resistance Probe (SRP), Medium Ion Scattering Spectroscopy (MEISS), Rutherford backscattering Spectroscopy (RBS), Secondary Ion Mass Spectrometry (SIMS), and High Resolution Transmission Electron Microscopy (HRTEM) and have measured resistivity of 250 ohms per square for 50 nm junction and a uniformity and repeatability of 1.1%. Modelling the implant and anneal-diffusion kinetics with molecular dynamic methods and measured defect counts have enabled us to design optimised processes. Surface peak concentrations of displaced atoms between 1E15 and 2E16 cm/sup -2/ in the Shallow Damage Region (SDR) and can suppress TED resulting in low leakage, high conductivity layers. The ultrashort spike anneal progressively fills vacancies and interstitial flow to the surface is the key defect annihilation process that controls TED. The SDR method using electron volt implants, rather than implants at several keV is now beginning to be used for advanced devices with low leakage, high speed and small dimensions.