Electronic transport across extended grain boundaries in graphene

Arnab K Majee,Zlatan Aksamija

doi:10.1088/2632-959x/ac0597

Abstract

Owing to its superlative carrier mobility and atomic thinness, graphene exhibits great promise for interconnects in future nanoelectronic integrated circuits. Chemical vapor deposition (CVD), the most popular method for wafer-scale growth of graphene, produces monolayers that are polycrystalline, where misoriented grains are separated by extended grain boundaries (GBs). Theoretical models of GB resistivity focused on small sections of an extended GB, assuming it to be a straight line, and predicted a strong dependence of resistivity on misorientation angle. In contrast, measurements produced values in a much narrower range and without a pronounced angle dependence. Here we study electron transport across rough GBs, which are composed of short straight segments connected together into an extended GB. We found that, due to the zig-zag nature of rough GBs, there always exist a few segments that divide the crystallographic angle between two grains symmetrically and provide a highly conductive path for the current to flow across the GBs. The presence of highly conductive segments produces resistivity between 102 to 104 Ω μm regardless of misorientation angle. An extended GB with large roughness and small correlation length has small resistivity on the order of 103 Ω μm, even for highly mismatched asymmetric GBs. The effective slope of the GB, given by the ratio of roughness and lateral correlation length, is an effective universal quantifier for GB resistivity. Our results demonstrate that the probability of finding conductive segments diminishes in short GBs, which could cause a large variation in the resistivity of narrow ribbons etched from polycrystalline graphene. We also uncover spreading resistance due to the current bending in the grains to flow through the conductive segments of the GB and show that it scales linearly with the grain resistance. Our results will be crucial for designing graphene-based interconnects for future integrated circuits.

Highlights

Over the last 50 years, persistent scaling of transistors in integrated circuits has been accompanied by shrinking the dimension of interconnects and vias, typically made of copper
We found that the resistivity is lowest for grain boundaries (GBs) with the largest Δ and the smallest Lcorr, which is counter-intuitive because roughness and short correlation lengths are often associated with adverse effects on transport
Since the conductivity of a nonstraight GB depends on the probability of finding a symmetric segment, a more wavy GB, which is caused by large roughness and small correlation length, exhibits the smallest resistivity, as we can see in figure 4(a)

Summary

Introduction

Over the last 50 years, persistent scaling of transistors in integrated circuits has been accompanied by shrinking the dimension of interconnects and vias, typically made of copper. Due to the increased surface roughness and grain boundary (GB) scattering, the resistivity of copper increases exponentially below 100 nm, which imposes a limit to further downscaling of copper interconnects [1]. This limitation has led to extensive research in finding a suitable alternative that can replace copper in the next-generation nanoelectronic devices and circuits. Controlled growth and nucleation processes using low-pressure CVD, adjusting content of oxygen on the surface of Cu substrate, and replacing methane with ethanol as carbon source have yielded single crystals up to a centimeter [5, 9, 10] and films up to 30 inches [11] in dimension

Methods

Results

Conclusion