Electronic Packaging Interfacial Strength Measurement and Delamination Investigation

Abstract

The microelectronics package is not only interconnecting the electronic signals from die to the printed circuit board (PCB), but also avoid the chips fracture during the manufacturing process or subsequent reliability testing stage. In general, the epoxy molding compound (EMC) are widely used in electronic packaging since its better processing capability and the lower circuit signal delay. However, the interfacial delamination in encapsulated silicon devices is a concern problem, especially for the interfaces between the copper lead-frame (LF) pads and EMC due to the weaker adhesion strength. To investigate the fracture of the copper leadframe/EMC interface of the Very Very-thin Quad Flat No-lead (WQFN) package, the double cantilever beam (DCB) experimental testing and numerical model based on the virtual crack closure technique methodology were constructed. Finally, a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> full factorial design with the analysis of variance (ANOVA) method is then employed to examine the effects of the main design parameters of the WQFN package (i.e., thickness of the epoxy molding compound (EMC), Die thickness, die bonding thickness, and die bonding size) on the strain energy release rate (SERR) between the copper and EMC under typical manufacturing thermal loading conditions.