Electron Tunnel Current through HfO[sub 2]∕SiO[sub 2] Nanometer-thick Layers with a Trapped Charge: Effects of Electron Incident Angle and Silicon Substrate Orientation

Abstract

A model for describing the electron transmittance and tunneling current in anisotropic MOS devices with a high‐k dielectric stack is studied by including the off‐diagonal effective‐mass tensor elements and the effect of coupling between transverse and longitudinal energies. The HfO2/SiO2 dual ultrathin layer is used as the gate oxide in an n+poly‐Si/oxide/Si capacitor. The main problem of using HfO2 is the charge trapping formed at the HfO2/SiO2 interface that can influence the performance of the device. In addition, without taking into account the effect of trap, the tunneling current in the n+‐poly Si/HfO2/SiO2/Si capacitor is almost zero at low bias voltage regime. Therefore, it is important to develop a model taking into account the presence of electron traps at the HfO2/SiO2 interface in the electron transmittance and tunneling current. In this paper, the effects of the electron incident angle and silicon substrate orientation on the transmittance and tunneling current are studied by utilizing the developed model.