Abstract
Open through silicon vias are direct vertical connections between different integration levels of a chip which provide higher performances per unit area in three-dimensional integrated circuits. The reliability of such structures in integrated circuits constitutes an important issue in microelectronics. This paper deals with electromigration reliability and lifetime evaluation of open copper through silicon vias. The model for electromigration induced voiding is proposed to describe the resistance change with time during the reliabilityanalysis. The model is derived by considering two distinctive failure phases, namely void initiation and void evolution, and their contributions on the complete interconnect lifetime estimation. Numerical calculations are carried out to reproduce the physical phenomenon. The resistance trace shows the typical initial flat constant part followed by non-linear time increase. Therefore, simulation results provide a good description of the time resistance change and, consequently, the electromigration lifetime evaluation in open copper through silicon vias.
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